Neo includes features you wouldn't expect from a hardware language in an easy to use package. Write concise logic with an expression-based syntax and functional programming features, and simplify complex designs with powerful and parameterizable types like tagged unions.
Neo's validator engine uses SMT-powered symbolic execution to catch your mistakes even before you've instantiated a module. Discover errors in your editor as you type, rather than waiting for slow simulator frameworks or FPGA tooling.
Neo generates human-readable SystemVerilog that is compatible with your simulation, synthesis, and validation toolchains. Your module hierarchy, wire names, and logic structure all all preserved, so you can use SystemVerilog tooling with ease.