Neo HDL

Appearance

Logic Values ​

Logic Values are the building blocks of logic in Neo. They are similar to a logic or wire in Verilog, but are strongly typed instead of just having a width and have timing information. This timing information is used to ensure soundness of pipelines.

Declaration ​

Logic values can be declared anywhere in a module, using the following syntax.

neo
logic my_name(0): Bits(32);

In this example, a logic value with name my_name will be created with a type of Bits(32) and a timing of 0. By default, timing is relative to a module's default trigger, which is provided to a module when it's instantiated. For more on the timing system, see TODO.

Logic values can also be given a value as part of their declaration:

neo
logic my_name(0): Bits(32) = some_other_value;

Assignment ​

Logic values can be statically assigned with an assign statement:

neo
assign target_value = some_other_value;

For complex logic expressions, a comb or seq block is used. This is equivalent to always_comb and always_ff in SystemVerilog. Expressions in logic blocks are allowed to generate more than one assignment. For example, an if expression could assign to two wires in each branch:

neo
comb {
  if condition {
    a = some_value;
    b = some_other_value;
  } else {
    a = some_other_value;
    b = some_value;
  }
}

In a comb block, it is required that all assignments have the same timing. In a seq block, it is required that all targets have a timing value that is one cycle later than the source.