Generator

The generator interpreter runs after the validator, and only if the validator produces no errors. It uses Intel's ROHD library to generate human-readable SystemVerilog that can be simulated or synthesized. The interpreter translates Neo code into ROHD library calls, constructing a graph that represents the hardware design. Any modules annotated with @top are considered entry points for the interpreter to start execution. These modules are not allowed to contain parameters. Each Neo module becomes a SystemVerilog module, and parameterized modules will have a SystemVerilog module for each set of parameters it has been instantiated with. Neo logic types are distilled down into simple wires. While this makes the generated SystemVerilog somewhat less readable (all wires are still well-named), it means that the generated SystemVerilog won't require advanced tooling no matter how complex the Neo design is.