Structs

Validator

The validator treats struct similarly to a collection of logic values not in a struct. Field accesses just return the corresponding underlying logic value, so individual assignment and use is unchanged from values not in a struct. When the struct as a whole is assigned, it is checked that each underlying value has not been assigned and then sets each one to assigned. Since field value timings are guaranteed to match, the struct's own timing can be checked.

Generator

Neo Struct's are interpreted as ROHD LogicStructures. Structs do not generate SystemVerilog structs. Instead, they will generate a wire for each field, with the name [var name]_[field name]. When used in module IO, the field wires will be concatenated into a single wire.

Example:

Source:

struct MyStruct {
  a: Int(32),
  b: Int(32),
}

@top
module Struct {
  input in(1): MyStruct,
  output out(1): MyStruct,
} {
  assign out = in;
  // Alternatively (generates same output):
  // assign out.a = in.a;
  // assign out.b = in.b;
}

Output:

module Struct (
input logic __defaultClock,
// Structs become a single wire in IO
input logic [63:0] in,
output logic [63:0] out
);
// Each struct gets a wire per field
logic [31:0] in_a;
logic [31:0] in_b;
logic [31:0] out_a;
logic [31:0] out_b;

// Wires are assigned individually, even if source code assigns as one
assign out_a = in_a;
assign out_b = in_b;

// Automatic boilderplate for (de)constructing the single wires from field wires
assign out = {out_b,out_a};
assign in_b = in[63:32];
assign in_a = in[31:0];
endmodule : Struct