Bits

The Bits type is used to represent non-integer bitstrings. It translates to a simple wire in generated Verilog.

Constructor

Bits(width: Nat)

Operators

The following operators translate directly to their Verilog counterparts: ==, !=, <<, >>, >>>, &, |. == and != return values of width 1, whereas other operators return a value with the same width as their operands (or the first operand, in the case of shifts).

The following unary operators also translate: ~, &, |. ~ preserves width, whereas & and | return single-width values.

## is used to concatenate two values. a ## b would translate to {a, b} in Verilog.

For Bits values of one width, && and || are available and behave the same as Verilog. They are limited to values of one width since treating any nonzero as true enables simple mistakes.

Methods

• asInt(): type cast to an Int of the same width.
• repeat(count: Nat): concatenate count instances of the value.
• zextend(width: Nat): zero extend the value to width width. Errors if width is less than the value's width.