Interpreter Architecture

Unlike other HDLs, Neo is an interpreted language. This may sound like an odd choice, but it results in powerful parameterization with a simple execution model. This design was inspired by embedded HDLs like Chisel, which are not an actual language, but rather a library for an off-the-shelf programming language. These libraries give you the ability to write a program than produces a hardware design upon execution. The benefit of this is that you can use the power of a full programming language to parameterize your designs, instead of having to rely on limited and complex generation primitives provided by a pure HDL like SystemVerilog. However, there are also significant drawbacks. Because they are just libraries, they have to work around the languages syntax and type system, resulting in many awkward edge cases. And, since they don't produce a hardware design until execution, there are two phases where you can get errors: the language's compiler can give errors such as invalid syntax or type mismatches, and you can get runtime errors for things like width mismatches, unnasigned wires, and so on.

By being an interpreted language designed only for generated hardware, Neo avoids the pitfalls of embedded HDLs while retaining the powerful parameterization ability. The syntax, exectution model, and type system were all designed to make describing hardware as powerful and intuitive as possible, so there's no conflicting keywords, operators, or types. Since it's interpreted, all errors in your design are reported at the same time with consistent formatting, clear messages, and points of origin that aren't cluttered by a runtime stack trace. This also enables all errors to be shown in your IDE as you type, instead of requiring a full execution of your program and then having to comb through the console output.

Neo is comprised of two interpreters. First, a symbolic validator checks parameterized modules and types for all possible input parameters. As long as it passes validation, no instantiation will ever throw an error. This enables you to write highly parameterized, resuable modules that are known to generate valid hardware with sound pipelines wherever they are used. If validation succeeds, the generator engine, powered by Intel's ROHD, produces human-readable and widely compatible SystemVerilog from your design. This engine is also compatible with ROHD's Simulator and Cosim, enabling rapid testing of your designs without having to deal with lengthy compilation steps.